This invention relates to a novel semiconductor device comprising a semiconductor body configuration which combines a plurality of HV-LDMOS transistors, a plurality of resistors, and a floating circuit well into a single structure.
The need is currently increasingly felt to integrate on a single silicon chip signal processing means and high-voltage components which operate efficiently and reliably.
In conventional LDMOS integrated circuits having floating wells, high-voltage interconnects are necessary to connect parts of the LDMOS transistors to circuit components within the floating well. In such structures, a level shift signal to the floating well is usually generated by a separate circuit and is brought to the floating well via current supplied via a cross-over. These high-voltage cross-overs create performance and fabrication problems.
A typical circuit for a floating well and level shifter from ground potential to that of the floating well is illustrated in FIGS. 1 to 4 which show circuit diagrams and a cross-section through a silicon wafer accommodating at least two insulated LDMOS level shift transistors and a floating well with circuitry. Such a device is constructed by means well known in the art and includes a substrate 7 of a first conductivity type, preferably with p polarity, a buried layer 8 with opposite conductivity, preferably with n+ polarity connected to an epitaxial layer 6, preferably of n- polarity. Above the buried layer 8, the epitaxial layer 6 is arranged. On the epitaxial layer 6, an oxide layer 9 is used on which a masking photoresist has been utilized to form a P-well portion 10 and an N-well portion 11 of the floating well. Subsequently, by appropriate masking, photolithography, and by ion implantation by means well known in the art, various p+ regions 12, 13, 14, 15, 16, and 17 and n+ regions 18, 19, 20, 21, 22, 23, 24, and 25 are formed with suitable metallization 26, 27, 28, 29, 30, 31, 32 and 33 to form the final structure shown in FIG. 4. Within the n-epitaxial layer, the regions 40 and 41 forming the body, 26 and 28 forming the source, and 27 forming the drain of the LDMOS transistor 3, and the regions 42 and 43 forming the body, 31 and 33 forming the source, and 32 forming the drain of the LDMOS transistor 5, as well as the p+ regions (p-iso regions) 12, 13, 14 and 15 separating the n-epitaxial layer 6 into isolated n-epitaxial regions 45, 46 and 47, are provided. The reference numerals 34 and 37 represent the gate electrodes.
In FIG. 3, the p+ regions 13 and 14 isolate the LDMOS devices 3 and 5, respectively, from the floating-well circuitry. The N-MOS device formed inside P-well 10, and the P-MOS device formed inside N-well 11 form part of the circuitry inside floating well 1.
Thus, as will be seen from FIGS. 3 and 4, the high voltage cross-overs make contact to circuitry in the floating well represented by PMOS 29, NMOS 30, n-well 11, and p-well 10, for example the high voltage interconnect 2, 4 is made from the drain contact 27, 32 of the LDMOS transistor 3, 5 to the N-well portion 11 and the P-well portion 10 of the floating well, crossing over the LDMOS transistor 3, 5 and junction 35, 36.
In such structures, the circuit in the well floats from 0 volts up to 1000 V. Turn on/turn off signals are generated by a voltage drop at the resistors R.sub.1 and R.sub.2 whereby V.sub.R1, V.sub.R2 is 0-20 volts. The high voltage interconnects are necessary to connect the drain terminals of the LDMOS transistors to the resistors R.sub.1 and R.sub.2 in the floating well. In such structures, a low voltage signal is provided to a level shifter which transfers it to a higher level. In a typical application, e.g. as a power converter, a voltage signal must be referenced to the output of an inverter stage. As this output voltages goes up and down, the signal applied floats with it. Because both the n-epitaxial layer and the p-substrate can support high voltage, the n-epitaxial regions can be tied to a node having essentially a positive DC voltage with respect to the output of, for example, a half-bridge circuit, and supply a signal between the control-and reference-electrode of an NPN or N-channel FET (MOS-FET, IGBT) device having its reference electrode essentially connected to the output of said half-bridge circuit, via a high-voltage crossover and the circuitry in the floating well. The term "reference electrode essentially connected to the output" is meant to cover a ripple on the DC voltage and an indirect connection of the reference electrode to the output of the half-bridge, e.g. via a current sense resistor or transistor, including cascoded switching (emitter, source or cathode switching). The term "control electrode" is meant to indicate a base and gate; and "reference electrode" indicates an emitter, source or cathode (N-channel).
FIGS. 1 and 2 show circuit diagrams which illustrate the input/output electronics of the floating well.
In FIG. 1, a bootstrap-capacitor 50 maintains a voltage between node 59 and 60 of typically between 5 and 20 Vdc; node 60 being positive with respect to node 59.
Assume the output voltage of comparator 53 to be low with respect to node 59, i.e. the voltage at the output of comparator 53 is at essentially the same voltage as node 59. By means of the non-inverting buffer formed by transistors 54, 55, 56 and 57, output node 58 will be pulled down to essentially the same voltage as node 59.
The state of the voltage at node 58 with respect to node 59 can be changed in the following way: By applying a pulse of voltage of well controlled magnitude to the control electrode of level-shift transistor 3, this device will sink a pulse of current into its drain 27. This will result in a pulse-shaped voltage drop across resistor 51, relatively independent of the momentary voltage level of node 59 and 60. As there is no current flow through the other level-shift transistor 5 at that time, the voltage across resistor 52 will be essentially 0. As soon as the difference between the voltage across resistors 51 and 52 exceeds the hysteresis-level built into comparator 53, the output of comparator 53 will go high with respect to node 59. The non-inverting buffer formed by the transistors 54, 55, 56 and 57 will consequently pull output node 58 up to essentially the same voltage as node 60, thereby making node 58 positive with respect to node 59.
After the voltage pulse at the control electrode of transistor 3 is over, the difference in voltage across resistors 51 and 52 returns to 0. Due to the hysteresis built into comparator 53, said comparator will retain the state of its output.
Conversely, if it is desired to change the state of node 58 and to return the voltage at node 58 to essentially the same voltage as node 59, a pulse of voltage of well controlled magnitude can be applied to the control electrode of transistor 5. This will result in a pulse-shaped flow of current into drain 32 of transistor 5, and consequently result in a voltage drop across resistor 52. As there is no flow of current into drain 27 of transistor 3, the voltage drop across resistor 51 will be 0. As soon as the difference between the voltages across resistors 51 and 52 exceeds the hysteresis-level built into comparator 53, the output of comparator 53 will go low with respect to node 59. The non-inverting buffer formed by the transistors 54, 55, 56 and 57 will consequently pull output node 58 down to essentially the same voltage as node 59.
After the voltage pulse at the control electrode of transistor 5 is over, the difference in voltage across resistors 51 and 52 returns to 0. Due to the hysteresis built into comparator 53, said comparator will retain the state of its output.
The circuit illustrated in FIG. 2 acts in an identical fashion, with the pulsating current sources formed by transistors 3 and 5 being replaced by the cascoded current sources formed by transistor 63 and 64, or 65 and 66, respectively.
Transistor 64 and 66 act as current sources, and can be standard N-MOS low-voltage devices or can even be replaced by low-voltage NPN bipolar devices. Transistors 63 and 65 are LDMOS devices, and are used to support the high voltage. FIG. 2 shows two embodiments of these LDMOS devices; one with the body connected to the source (transistor 63) and one with the body connected to ground (transistor 65).
As will be appreciated, problems arise when attempts are made to place such conventional structures on a single silicon chip. Properties of the drift region make it very difficult to put a line across this region to connect the high-voltage area of the floating well to the transistor. Additionally, the high voltage interconnects adversely affect the high voltage junction, require at least two additional mask steps increasing fabrication costs, and necessitate a larger chip size.